A key challenge in integrating high performance bipolar transistors into a BiCMOS circuit, as is utilized in high performance mixed signal applications, is to form high performance bipolar transistors without adversely affecting the performance of CMOS transistors and without introducing excessive process complexity during the manufacturing. While various methods of manufacturing bipolar transistors have been known in the art, not all of them can be employed in BiCMOS circuits since many of them are incompatible or substantially affect the performance of CMOS devices adversely. Only integration schemes that fully protect the performance CMOS devices can successfully integrate high performance bipolar transistors with CMOS devices without degradation of CMOS circuit performance.
To achieve high performance in a bipolar transistor, factors affecting the critical performance parameters of the bipolar transistor need to be considered such as the unit current gain frequency (fT), which is the frequency at which the current gain becomes 1, and the maximum oscillation frequency (fMAX), which is the maximum frequency at which there is still power gain. The two performance parameters, fT and fMAX, critically depend on parasitic parameters of the bipolar transistor structure. The unit current gain frequency is inversely proportional to the product of base transit time (tb) and collector-base capacitance (Ccb), that is, fT∝1/(tb×Ccb). Since the base transit time increases with the thickness of the intrinsic base, high temperature must be avoided to minimize the thermal broadening of the intrinsic base. The maximum oscillation frequency is proportional to the square root of the unit current gain frequency and is inversely proportional to the produce of base resistance (Rb), which is the sum of both intrinsic and extrinsic resistance, and collector-base capacitance (Ccb), i.e., fMAX∝(fT/(Rb×Ccb))0.5. To increase fMAX, fT needs to be increased and both Rb and Ccb need to be decreased. Self-alignment of an extrinsic base to an emitter is thus preferred to reduce the base resistance, Rb, and consequently, to increase fMAX.
Formation of raised extrinsic base in prior art bipolar transistors typically employs a chemical mechanical planarization (CMP) process. However, integration of raised extrinsic base bipolar transistors with CMOS devices in a BiCMOS circuit faces challenges since the patterned gate electrodes of CMOS devices introduces topographical variations, that is, differences between the height of the bipolar structures and the CMOS structures. These differences are on the order of the height of the gate electrodes of CMOS devices, typically in the range from about 100 to about 250 nm. The height of at least one type of structure is typically adjusted with an accompanying compromise in the device performance.
As disclosed in the U.S. Pat. No. 6,780,695, Chen et al. circumvents the problem of height differences between the device types by depositing a sacrificial polysilicon layer in a bipolar transistor area concurrently with a deposition of a gate polysilicon in the CMOS device area. The overall structure is planarized with a polysilicon placeholder material. A bipolar transistor is formed by removing the sacrificial polysilicon to expose an active silicon region, forming an intrinsic base and an emitter pedestal, and then forming an extrinsic base that is confined within the opening of the sacrificial polysilicon layer. While Chen et al., enables an integration scheme for high performance BiCMOS circuit, the complexity of the process increases by the introduction of additional steps, notably, the deposition of polysilicon placeholder material and planarization, deposition of a polysilicon layer over a base oxide and subsequent planarization utilizing an additional lithographic patterning.
Therefore, there exists a need to enable a high performance bipolar transistor with the benefits of self-aligned raised extrinsic base in a BiCMOS structure that contains at least one CMOS device.
There also exists a need to provide a high performance BiCMOS structure with minimum process complexity without compromising the performance of either the bipolar transistor or CMOS devices.